Hardware Acceleration

OCUDU India supports offloading CPU-heavy stages of the upper-PHY from the host to dedicated vRAN accelerators. The goal is better latency and throughput on the same hardware budget, with the freedom to fall back to a pure-software path when no accelerator is available.

Design principles

• Software parity. The HW and SW paths implement the same interfaces; no functional difference observable from MAC or above.
• Configuration-driven. Choose path via DU YAML at startup. No code changes, no runtime toggling.
• Unified metrics. Every enqueue/dequeue on the HW path emits the same metric fields the SW path emits. A/B comparisons use one log format.
• Batched dispatch. Operations are accumulated per-TB and submitted to the accelerator as a single burst, amortising DPDK per-call cost.
• On-device state. HARQ soft-buffer data stays on the accelerator between transmissions; the host tracks only context lifecycle.

Supported accelerators

When to enable acceleration

• High-PRB-count cells (80–100 MHz) where software LDPC becomes the upper-PHY bottleneck.
• Multi-cell hosts where freeing CPU on the upper-PHY increases cell density per server.
• Tail-latency-sensitive deployments LDPC decode tail latency compresses substantially on hardware.

What to read next

• First time enabling HWACC? Start with the ACC100 guide it covers prerequisites, kernel/VFIO setup, YAML, build flags, and a deployment checklist.
• Already running HWACC and want to understand the numbers? Jump to the benchmark results for the A/B comparison.
• Adding a new accelerator backend? See the contributing guide for how to file an RFC.